搜索资源列表
photo_verilog
- verilog开发的电子相册系统，是基于Altera的FPGA芯片和IP核的设计！-Verilog developed electronic album system is based on Altera s FPGA chip and IP core design!
SOPCVGAIP
- 基于sopc的vga ip核设计参考文档-Based on SOPC vga ip-core design of the reference documentation
BaselineJPEGSoftwareCodecCodes
- In term project, we will take the baseline JPEG codec in ARM-based platform system as an example to practice the design flow in SoC. We divide the project into three parts, and the goal of each part is described as follow. Part I: Design a baseli
can.tar
- can控制器IP核，verilog语言描述实现。含测试例-can controller IP core, verilog language described realize. Containing the test cases
USBipcore
- usb1.1 ip核，使用verilog编写-usb1.1 ip nuclear, prepared using the Verilog
VERILOG_VERSION_PIC16C57
- VERILOG VERSION PIC16C57 是一个用于FPGA模拟PIC16C57的IP核，有帮助文件，介绍了如何测试使用这个IP核。用VERILOG语言编写的。-VERILOG VERSION PIC16C57 is a PIC16C57 for FPGA simulation of the IP core, has helped document describes how to test the use of the IP core.
FPGA_8008
- pci pci转local bus总线的应用，使用IPcore alter器件-pci pci convert local bus application,use alter IP core
DW8051_ALL
- 包中包括, DW8051完整的Verilog HDL代码 两本手册: DesignWare Library DW8051 MacroCell, Datasheet DesignWare DW8051 MacroCell Databook 三篇51论文: 基于IP 核的PSTN 短消息终端SoC 软硬件协同设计 Embedded TCP/ IP Chip Based on DW8051 Core 以8051为核的SOC中的万年历的设计 -DW8051 is desi
08Tutorial3
- tutorial of xilinx ip core
AES
- AES算法的verilog代码，即AES算法IP核-ip core for AES
dsp_core
- 可用于FPGA的DSP IP核，嵌入式必备-Can be used for FPGA-DSP IP core, embedded essential
spi_op_core
- spi controller SPI IP core
SmartSOPC_Component
- smartSOPC NIOS IP core，周立功FPGA实验箱IP核-smartSOPC NIOS IP core, Zhou Ligong FPGA experimental box IP core
USB_IP
- 介绍了采用FPGA实现USB2.0 IP核的详细方法和步骤以及仿真方法-This paper introduces an FPGA to achieve the USB2.0 IP core in detail the methods and steps as well as the simulation method
vhdl-arm-core
- 用vhdl语言实现arm内核，压缩包中有19个代码共同组成这个arm内核，程序比较大，应用时要注意那个代码是顶层实体。用quartus2软件即可打开仿真。-Vhdl language used arm core, compressed package code of 19 common core component of this arm, procedures, and application code should be noted that top-level entity. Used t
SRAM_Controller
- Altera University Program的Avalon总线IP核，SRAM控制代码，可以解压后直接挂载在Avalon总线上 -Altera University Program of the Avalon bus IP core, SRAM control code can be directly mounted after decompression in the Avalon bus
Quartus
- Quartus中fft ip core的使用.txt-Fft ip core in Quartus use. Txt
8086
- 基于FPGA的8086/8088 IP核-8086/8088 FPGA IP Core
VHDLAVRIPcore
- 使用VHDL语言写的AVR单片机IP核， 可以直接使用，已经经过验证， 十分珍贵哦-Written in VHDL language using the AVR microcontroller IP core, can be used directly, has proven very valuable oh
myfir
- 利用fir滤波器ip-core设计滤波器，数据为16bit，速率为61.44mhz，工作时钟为245.76mhz-The use of fir filter ip-core design of filters, the data for the 16bit, rate 61.44mhz, working clock 245.76mhz